FIFO, handshake synchronizers a challenge for CDC analysis
13th Nov 2006, 21:46 GMT
Among the many verification challenges confronting system-on-chip designers these days, clock domain crossings (CDCs) rank near the top in difficulty. Two particularly troublesome CDC-related issues involve FIFO- and handshake-based synchronization mechanisms. Both can be difficult or impossible to verify accurately using simulation. A new class of CDC tool, using static analysis techniques, offers the first effective automated solution to these problems. The new tools combine functional and structural analysis to identify and verify FIFO and handshake synchronizers while weeding out the false violations that plague traditional CDC tools.
FIFO, handshake synchronizers a challenge for CDC analysis related news:
- Stocks to Watch, Nov. 14: Abercrombie & Fitch and CDC — FOXNews.com
- Flu Vaccine Distributors Support National Influenza Vaccination Week — Health News from Medical News Today
- Structural modelling and analysis is upgraded — Engineering Design Software latest news on Engineeringtalk
- AFC roundup — Cincinnati Enquirer - Sports All
- Parent Group Responds to CDC Announcement on Flu Supply — U.S. Newswire Releases
- Madonna adoption challenge heard — BBC News | Entertainment | World Edition
- Court rejects IR challenge — The Age News Headlines
- Indonesian treaty signed, sealed and delivered — The Age World Headlines
- Zune launches iPod challenge — Seattle Post-Intelligencer: Business News
- Madonna adoption challenge begins — BBC News | Latest Published Stories | World Edition
Latest news from Wireless Net DesignLine:
- Long road ahead for near-field chips
- Wireless HDMI effort amasses support
- TI, Certicom collaborate on RFID
- WIRELESS SYSTEMS: SDR platform armed for the military
- WIRELESS NETWORKS: RapidIO serial buffer debuts
- Quality clash in the home network
- TI launches SDR development platform
- Speed up downconverter implementation with rapid prototyping
- Wireless nets get SoC
- Unleash modular base station design with Serial RapidIO