Programmable Logic DesignLine News Archive
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- Multi-processor and reconfigurable computing
- Nanomembrane makes super conductor
- Huge FPGA synthesis gap seen
- Tensilica adds configured processors to its stable
- SystemC assertions go 'native'
- Tool generates verification plans from design specs
- Tenison's VTOC product supporting VHDL, mixed languages
- French firm adds SystemVerilog assertion support to debug tool
- Infineon expands 8-, 16-, and 32-bit MCUs for industrial apps.
- Texas startup formed to take ARM chips to market
- Israeli scientists produce nanoscale wires from proteins
- MCUs tout PWM with 150 psec resolution
- Deja Vu (Did somebody just say that?)
- Using object-oriented methods to achieve C++'s promise: Part 2
- Synopsys posts profit, fifth straight quarter of revenue growth
- Improve your root-mean calculations
- MCUs feature 180-degree control for motors in appliance apps
- Intel readies dual-core Xeon for embedded apps
- Cyclone II FPGAs support extended temperature range
- USB-stick development tool for TI's MCU goes for $20
- Quadros dual-mode RTOS ports to Freescale's Coldfire MPUs
- Hardware debug tracer targets ARM processors
- FPGA tool suite promises intuitive environment
- FPGA-based kit accelerates adoption of software-defined radio modems
- Demystifying UML
- eInfochips offering silicon, system validation
- Elliptic Semiconductor ports security IP cores to Lattice FPGAs
- Optimality study of logic synthesis for LUT-based FPGAs
- Using object-oriented methods to achieve C++'s promise: Part 3
- Two ARM-Core MCU targets time-critical industrial control apps
- What are framers and mappers?
- Single chip controller simplifies embedded Ethernet connectivity
- Anyone need a world-leading ASIC design team?
- Programmability tunes analog functionality
- FPGAs consumed by power issues
- Using design patterns to identify and partition tasks in an RTOS environment: Part 3
- SystemC finds new horizons
- The 'what' and 'why' of transaction level modeling
- ESL startup Carbon Design Systems inks deals with European distributors
- Firms partner on PCIe verification
- Actel offers development kit for ARM7-enabled FPGAs
- Celoxica teams with software writers to drive ESL
- 16-bit MCU boasts 1.8 mW/MIPS power consumption
- Spiral FPGA architectures?
- How to achieve fast timing closure on FPGA designs
- Simulating and debugging multicore behavior
- French startup offers compact 32-bit RISC
- Israeli reseachers build new type of nanotube
- Vast Technology offers three more virtual ARM processors
- Xilinx hit by substrate shortages
- Why is grass green and tomatoes red?
- Actel expands PSC design infrastructure
- Putting Multicore Processing in Context: Part 2
- Startup donates compliance checker to OCP-IP
- Novas tool lets designer see data from debugging
- Xilinx plots beefy 65-nm FPGA family
- FPGA-based platform speeds in-vehicle testing
- Will I see you at the Multicore Expo?
- Partners to rev PowerPC
- Vendors warm to SystemVerilog
- Interoperability test lifts Serial RapidIO
- Increasing visibility in FPGA prototypes and emulators
- French company offers embedded FPGA
- Cadence "knowledge system" targets verification bottleneck
- LSI scraps RapidChip ASIC line (plans to sell DSP unit)
- Data buffering with FPGAs in a disproportional line rate environment
- PIC MCU line offers certified full-speed USB 2.0
- 8051-based MCU family boasts 5 x 5 mm form factor
- Using dense multi-layer packages in high-performance systems
- Accelerated Technology's Nucleus RTOS supports Tensilica's new Diamond CPU cores
- Virtual system prototypes ease design
- System synchronization styles and trends
- Siloti from Novas: what a great idea!
- Details emerge on western U.S. nanotech effort
- ESL startup Bluespec raises $4.5 million
- Freescale unleashes microcontroller roadmap
- Xilinx launches ESL initiative
- Summit Design offers 'personal edition' of SystemC IDE on Web
- Implementing H.264 video compression on a software configurable processor
- Know any good books?
- Mixed-signal FPGA integrates soft ARM7 IP core
- European firms partner to ease UML/SysML management
- Register description language available through open source
- Throwing someone off a tower for science!
- Reality TV for FPGA design engineers!
- Applying distributed system concepts to embedded multiprocessor designs: Part 3
- TI-Altera solution achieves PCI-SIG compliance
- Using soft cores to balance HW/SW needs in multicore FPGA designs
- IEEE recognizes Cadence for SystemVerilog contributions
- Tensilica offers free Diamond Standard core development tools
- 8-bit MCUs target digital audio-visual systems
- I'm off to see the wizard...
- EDA startup moves binaries into FPGAs
- Rivals may vie at Multicore Expo
- Tool suite spans STMicro MCUs
- Transaction-level models (TLMs) offer new deal for EDA
- The 'what and why' of transaction-level modelling (TLM)
- Multicore state-diagram tool supports softcore FPGAs
- The Multicore Expo Draws Nigh!
- Lattice agrees $3.5 million to settle class action